2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R_post
0
-1
R_post
0
A_post
-1
R_post
0
-1
A_post
R_post
0
A_0
-1
A_post
0
-1
A_0
A_post
0
NBuffers_0
-1
NBuffers_post
0
-1
NBuffers_0
NBuffers_post
0
NLocBuffer_0
-1
NLocBuffer_post
0
-1
NLocBuffer_0
NLocBuffer_post
0
R_0
-1
R_post
0
-1
R_0
R_post
0
istemp_0
-1
istemp_post
0
-1
istemp_0
istemp_post
0
1
0
-1
istemp_post
istemp_post
0
istemp_post
-1
istemp_post
0
-1
istemp_0
istemp_0
0
istemp_0
-1
istemp_0
0
-1
R_post
R_post
0
R_post
-1
R_post
0
-1
R_0
R_0
0
R_0
-1
R_0
0
-1
NLocBuffer_post
NLocBuffer_post
0
NLocBuffer_post
-1
NLocBuffer_post
0
-1
NLocBuffer_0
NLocBuffer_0
0
NLocBuffer_0
-1
NLocBuffer_0
0
-1
NBuffers_post
NBuffers_post
0
NBuffers_post
-1
NBuffers_post
0
-1
NBuffers_0
NBuffers_0
0
NBuffers_0
-1
NBuffers_0
0
-1
A_post
A_post
0
A_post
-1
A_post
0
-1
A_0
A_0
0
A_0
-1
A_0
0
2.4
0
1
A_post
0
R_post
0
-1
R_post
0
A_0
0
R_0
0
-1
R_0
0
2
2
0
0
0
1
1
A_post
0
R_post
0
-1
R_post
0
A_0
0
R_0
0
-1
R_0
0
1
2
2
1
0
2
0
0
0
1
0
2
-4
0
-5
1
-6
-8
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T2Cert
1.0